The present invention relates to output driver circuits, and more particularly, to techniques and circuits for pre-charging and discharging an output driver circuit.
Generally, interface circuitry such output buffer circuits are used to amplify and/or condition signals for transmission. An output buffer circuit is typically required to drive an output signal at the appropriate levels for a given transmission link or input and output (I/O) standards so that the output signal may be used by other connected circuits.
Buffer circuits are often designed to operate over a specific operating voltage and current range. For example, many driver circuits are designed to operate within I/O guidelines that specify the minimum and maximum operating voltage levels required for proper operation of the buffer circuit with other circuits. Such guidelines are generally derived from groups and/or agencies that set standards usable by the industry as a whole. There are many standards (e.g., LVTTL, LVCMOS, SSTL, HSTL, PCI, and PCI-X) for various interface applications. For example, low-voltage transistor-transistor logic (LVTTL) requires a 1.8V, 2.5V, or 3.3V input voltage levels depending on the needs of a given circuit application.
Integrated circuits and electrical components are usually designed with operating margins to allow them to operate somewhat outside their intended operating parameters without permanent damage. For example, most buffer circuit designs allow a buffer circuit to sustain momentary fluctuations in voltage and current beyond their operational specifications without incurring damage that can lead to permanent performance degradation. Unfortunately, as integrated circuit manufacturers shrink the size of the integrated circuits through the use of more advanced silicon processes, many of the once robust circuits are now becoming susceptible to damage and permanent degradation. To meet industry form, fit, and function requirements, such smaller less robust integrated circuits are usually specified in, and expected to operate in environments previously supported by the larger more robust integrated circuits. For example, a buffer circuit originally designed to accommodate 3.3V with built-in operating margins may begin having failures caused in part by decreasing operating margins due to the smaller, thinner oxide and shorter transistor channel components. The problem is further exacerbated when designing an integrated circuit using a more advanced silicon process, due to the fact that the advanced silicon process may no longer offer the higher voltage tolerant transistors, previously available with less advanced silicon processes.
One operating concern for transistors is handling momentary voltage and current transitions that may exceed their specified ratings without permanent degradation. For example, some transistor degradation mechanisms like Hot Carrier Injection (HCI) and Negative Bias Temperature Instability (NBTI) degrade the gate oxide of the transistor and serve to reduce its performance by increasing the threshold voltage as well as reducing the drive capability of the transistor. HCI is a transistor degradation mechanism which primarily afflicts the NMOS transistors of the circuit. It is caused due to the injection of hot electrons into the gate of the transistor causing charge trapping in the gate oxide and hence degradation in performance. Hot carriers are the results of high energy electrons which form the drain current as well as the electron-hole pairs generated at the drain end due to impact ionization. These degradation mechanisms become even more evident with decreasing transistor gate size.
There is therefore a need for circuits and methods to reduce the electrical stress imposed on integrated circuit transistors in order to improve integrated circuit operational performance and robustness. There is also a need for circuits and methods to support a higher voltage operation than the devices derived from a given silicon process are specified for, without permanent degradation.